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ORC-2178: [C++] Add basic RISC-V build system and CPU detection support#2639

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zhanchangbao-sanechips:rvvopt
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ORC-2178: [C++] Add basic RISC-V build system and CPU detection support#2639
zhanchangbao-sanechips wants to merge 2 commits into
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zhanchangbao-sanechips:rvvopt

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@zhanchangbao-sanechips

@zhanchangbao-sanechips zhanchangbao-sanechips commented Jun 11, 2026

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What changes were proposed in this pull request?

add the minimum to get RISC-V support in the build system and CPU detection. This is needed before can start add RVV-optimization.

changes:

  • Added BUILD_ENABLE_RVV CMake option (off by default)
  • Added rv64gcv toolchain detection in ConfigSimdLevel.cmake
  • ORC_USER_SIMD_LEVEL now accepts RVV or NONE

If RVV isn't available, it just falls back to scalar code.

Why are the changes needed?

ORC doesn't know anything about RISC-V. This is just the groundwork so follow-up patches can actually use RVV. (https://issues.apache.org/jira/browse/ORC-1971)

How was this patch tested?

  • Tested on a Sophgo SG2044 board with GCC 14.2.0
  • Built with -DBUILD_ENABLE_RVV=ON, config passed
  • Setting ORC_USER_SIMD_LEVEL=NONE properly masks out RVV

@wgtmac

wgtmac commented Jun 11, 2026

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Thanks for your interest in working on this! Before proceeding, I have some general questions:

  • Does it support a wide range of RISC-V family or just specific chips?
  • Is it possible to set up a CI workflow for this? Not sure if Github action already have this.
  • How do we want to maintain this in the future?

cc @dongjoon-hyun @ffacs

@zhanchangbao-sanechips

zhanchangbao-sanechips commented Jun 11, 2026

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Thanks for your interest in working on this! Before proceeding, I have some general questions:

  • Does it support a wide range of RISC-V family or just specific chips?
  • Is it possible to set up a CI workflow for this? Not sure if Github action already have this.
  • How do we want to maintain this in the future?

cc @dongjoon-hyun @ffacs

Thanks for your questions.

  • It targets standard RISC-V Vector Extension 1.0 (RVV 1.0), not a specific chip, so it works across any RVV-compliant core regardless of vector register width. I've tested on two different platforms: SG2044 and K1. The detection logic behaves consistently across both. It's not tied to any specific chip.
  • GitHub Actions doesn't have native RISC-V runners yet. However, we can run tests under QEMU user-mode emulation (e.g., using qemu-riscv64-static). I can help set up a basic CI workflow that cross-compiles ORC for RISC-V and runs the test suite in emulation. It's slower than native but works on standard GitHub-hosted runners.
  • The code in this PR is intentionally minimal—just build flags and CPU detection. I plan to follow up with actual RVV optimizations in later PRs.Additionally, my company is currently investing in RISC-V porting and optimization work internally. So I intend to maintain this. This PR is part of a longer-term effort—we have ongoing plans to add RVV-accelerated bit unpacking and other SIMD optimizations. So this isn't a one-off contribution; there will be continued engineering resources behind it.

@zhanchangbao-sanechips zhanchangbao-sanechips force-pushed the rvvopt branch 2 times, most recently from 8f6bf91 to 156c50c Compare June 16, 2026 07:53
@zhanchangbao-sanechips

zhanchangbao-sanechips commented Jun 16, 2026

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Thanks for your interest in working on this! Before proceeding, I have some general questions:

  • Does it support a wide range of RISC-V family or just specific chips?
  • Is it possible to set up a CI workflow for this? Not sure if Github action already have this.
  • How do we want to maintain this in the future?

cc @dongjoon-hyun @ffacs

Thanks for your questions.

  • It targets standard RISC-V Vector Extension 1.0 (RVV 1.0), not a specific chip, so it works across any RVV-compliant core regardless of vector register width. I've tested on two different platforms: SG2044 and K1. The detection logic behaves consistently across both. It's not tied to any specific chip.
  • GitHub Actions doesn't have native RISC-V runners yet. However, we can run tests under QEMU user-mode emulation (e.g., using qemu-riscv64-static). I can help set up a basic CI workflow that cross-compiles ORC for RISC-V and runs the test suite in emulation. It's slower than native but works on standard GitHub-hosted runners.
  • The code in this PR is intentionally minimal—just build flags and CPU detection. I plan to follow up with actual RVV optimizations in later PRs.Additionally, my company is currently investing in RISC-V porting and optimization work internally. So I intend to maintain this. This PR is part of a longer-term effort—we have ongoing plans to add RVV-accelerated bit unpacking and other SIMD optimizations. So this isn't a one-off contribution; there will be continued engineering resources behind it.

Thanks for your interest in working on this! Before proceeding, I have some general questions:

  • Does it support a wide range of RISC-V family or just specific chips?
  • Is it possible to set up a CI workflow for this? Not sure if Github action already have this.
  • How do we want to maintain this in the future?

cc @dongjoon-hyun @ffacs

Thanks for your questions.

  • It targets standard RISC-V Vector Extension 1.0 (RVV 1.0), not a specific chip, so it works across any RVV-compliant core regardless of vector register width. I've tested on two different platforms: SG2044 and K1. The detection logic behaves consistently across both. It's not tied to any specific chip.
  • GitHub Actions doesn't have native RISC-V runners yet. However, we can run tests under QEMU user-mode emulation (e.g., using qemu-riscv64-static). I can help set up a basic CI workflow that cross-compiles ORC for RISC-V and runs the test suite in emulation. It's slower than native but works on standard GitHub-hosted runners.
  • The code in this PR is intentionally minimal—just build flags and CPU detection. I plan to follow up with actual RVV optimizations in later PRs.Additionally, my company is currently investing in RISC-V porting and optimization work internally. So I intend to maintain this. This PR is part of a longer-term effort—we have ongoing plans to add RVV-accelerated bit unpacking and other SIMD optimizations. So this isn't a one-off contribution; there will be continued engineering resources behind it.

I add a RISC-V CI workflow：this.#2644

ffacs
ffacs reviewed Jun 16, 2026
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Comment thread c++/src/CpuInfoUtil.cc Outdated
int64_t LinuxParseRiscvIsa(const std::string& values) {
int64_t flags = 0;
// RISC-V ISA string like "rv64imafdcv" contains 'v' for vector extension
if (values.find('v') != std::string::npos) {

@ffacs ffacs Jun 16, 2026

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This is always true

@zhanchangbao-sanechips zhanchangbao-sanechips Jun 17, 2026

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Thanks for the reminder. I've updated the implementation to use getauxval(AT_HWCAP) to detect HWCAP_RISCV_RVV instead of parsing the ISA string.

@zhanchangbao-sanechips
ORC-2178: [C++] Fix RVV detection by using getauxval(AT_HWCAP)
6f9361a 
The previous implementation parsed /proc/cpuinfo's "isa" field and
checked for the presence of 'v'. This is incorrect because all RISC-V
ISA strings start with "rv...", so 'v' in the prefix always matches.

Now use getauxval(AT_HWCAP) and HWCAP_RISCV_RVV to detect the vector
extension at runtime.
@ffacs ffacs closed this in 56e88ba Jun 28, 2026
@ffacs

ffacs commented Jun 28, 2026

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Merged. Thanks @zhanchangbao-sanechips @wgtmac ~

@zhanchangbao-sanechips

zhanchangbao-sanechips commented Jun 29, 2026

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Merged. Thanks @zhanchangbao-sanechips @wgtmac ~

Appreciate your review and merge. I will send follow-up PRs after the RVV decoder implementation lands to further polish RISC-V support.

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